In portions of a conventional application specific integrated circuit (ASIC), Platform ASIC, other field programmable gate array (FPGA) or like designs, one to several input gates within the designs are tied to fixed values of logical zero (i.e., ground or VSS) or logical one (i.e., power or VDD). An example application for fixing gate inputs is a Joint Test Action Group (JTAG) identification (ID) number, as illustrated in FIG. 1. The example illustrates a JTAG ID register number (3:0) of binary “0010”.
Very late in a design flow, or even after a design is taped out and prototypes have been tested in context with the intended systems, small bugs are commonly found in the design. Enhancements are also commonly planned for the design. Appropriate methodologies are available today to implement the bug fixes and the enhancements. However, changes to the design are difficult to implement with only minor changes to the layout.
Even if corrections and real functional enhancements can be achieved with changes in only a single metal layer, changing tied gate inputs, like the JTAG ID, can easily result in changes to multiple metal layers. For example, swapping a route for a gate input from VDD or VSS to an opposite value can be blocked by the routing of other signals. Therefore, an effort to reduce functional changes to a minimum number of metal layers is often wasted because reversing tied-high and tied-low gate inputs can result in changing many metal layers.
Currently the cost of having to implement a change, which could be done in a single metal layer, is the cost of changing several metal layers to account for tie-high/tie-low changes. No solution is currently in place that could guarantee that changes for tied-high and tied-low gates can be implemented in a single metal layer. The cost of a change in each additional metal layer in small geometry technologies becomes more unacceptable.